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| d a t a sh eet product speci?cation file under integrated circuits, ic06 2000 mar 15 integrated circuits 74ahc595; 74ahct595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state
2000 mar 15 2 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 features esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v cdm eia/jesd22-c101 exceeds 1000 v balanced propagation delays all inputs have schmitt-trigger actions inputs accept voltages higher than v cc for ahc only: operates with cmos input levels for ahct only: operates with ttl input levels specified from - 40 to +85 c and from - 40 to +125 c. applications serial-to-parallel data conversion remote control holding register. description the 74ahc/ahct595 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74ahc/ahct595 is an 8-stage serial shift register with a storage register and 3-state outputs. the shift register has separate clocks. data is shifted on the positive-going transitions of the sh cp input. the data in each register is transferred to the storage register on a positive-going transition of the st cp input. if both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. the shift register has a serial input (d s ) and a serial standard output (q 7 ) for cascading. it is also provided with asynchronous reset (active low) for all 8 shift register stages. the storage register has 8 parallel 3-state bus driver outputs. data in the storage register appears at the output whenever the output enable input ( oe) is low. quick reference data gnd = 0 v; t amb =25 c; t r =t f 3.0 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; ? (c l v cc 2 f o ) = sum of outputs; c l = output load capacitance in pf; v cc = supply voltage in volts. 2. the condition is v i = gnd to v cc . 3. all 9 outputs switching. symbol parameter conditions typical unit ahc ahct t phl /t plh propagation delay c l = 15 pf; v cc =5v sh cp to q 7 4.0 3.8 ns st cp to q n 4.2 4.0 ns mr to q 7 4.4 4.6 ns c i input capacitance 3.0 3.0 pf f max maximum clock frequency 170 170 mhz c pd power dissipation capacitance c l = 50 pf; f = 1 mhz; notes 1, 2 and 3 180 190 pf 2000 mar 15 3 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 function table see note 1. note 1. h = high voltage level; l = low voltage level; - = low-to-high transition; = high-to-low transition; x = dont care; nc = no change; z = high impedance off-state. ordering information input output function sh cp st cp oe mr d s q 7 q n x x l l x l nc a low level on mr only affects the shift registers x - l l x l l empty shift register loaded into storage register x x h l x l z shift register clear. parallel outputs in high impedance off-state. - xlhhq 6 nc logic high level shifted into shift register stage 0. contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal q 6 ) appears on the serial output (q 7 ). x - lhxncq n contents of shift register stages (internal q n ) are transferred to the storage register and parallel output stages -- lhxq 6 q n contents of shift register shifted through. previous contents of the shift register is transferred to the storage register and the parallel output stages. type number packages temperature range pins package material code 74ahc595d - 40 to +125 c 16 so plastic sot109-1 74ahc595pw 16 tssop plastic sot403-1 74AHCT595D 16 so plastic sot109-1 74ahct595pw 16 tssop plastic sot403-1 2000 mar 15 4 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 pinning pin symbol description 1, 2, 3, 4, 5, 6, 7 and 15 q 1 , q 2 , q 3 , q 4 , q 5 , q 6 , q 7 and q 0 parallel data output 8 gnd ground (0 v) 9q 7 serial data output 10 mr master reset (active low) 11 sh cp shift register clock input 12 st cp storage register clock input 13 oe output enable input (active low) 14 d s serial data input 16 v cc dc supply voltage handbook, halfpage q 1 q 2 q 3 q 4 q 5 q 6 q 7 gnd v cc q 0 d s oe sh cp st cp q 7 ' 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 595 mna551 mr fig.1 pin configuration. handbook, halfpage oe mr 9 15 1 2 3 4 5 6 7 13 10 14 11 12 mna552 q 1 q 0 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' d s st cp sh cp fig.2 logic symbol. 2000 mar 15 5 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 handbook, halfpage mna553 15 9 1 2 3 4 5 6 7 1d 2d c1/ 10 11 14 c2 12 13 en3 srg8 r 3 fig.3 iec logic symbol. handbook, halfpage mna554 3-state outputs 8-bit storage register 8-stage shift register q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' 14 151 234567 9 d s sh cp st cp oe 11 10 12 13 mr fig.4 functional diagram. handbook, full pagewidth stage 0 stages 1 to 6 stage 7 ff0 d cp q r latch d cp q ff7 d cp q r latch d cp q mna555 dq q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' q 0 d s st cp sh cp oe mr fig.5 logic diagram. 2000 mar 15 6 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 handbook, full pagewidth sh cp d s st cp mr oe q 0 q 1 q 6 q 7 q 7 z-state z-state z-state z-state mna556 fig.6 timing diagram. 2000 mar 15 7 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so packages: above 70 c the value of p d derates linearly with 8 mw/k. for tssop packages: above 60 c the value of p d derates linearly with 5.5 mw/k. symbol parameter conditions 74ahc 74ahct unit min. typ. max. min. typ. max. v cc dc supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 v v i input voltage 0 - 5.5 0 - 5.5 v v o output voltage 0 - v cc 0 - v cc v t amb operating ambient temperature see dc and ac characteristics per device - 40 +25 +85 - 40 +25 +85 c - 40 +25 +125 - 40 +25 +125 c t r , t f input rise and fall ratios ( d t/ d v) v cc = 3.3 0.3 v -- 100 --- ns/v v cc =5 0.5 v -- 20 -- 20 ns/v symbol parameter conditions min. max. unit v cc dc supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i ik dc input diode current v i < - 0.5 v; note 1 -- 20 ma i ok dc output clamping diode current - 0.5 > v o >v cc + 0.5 v; note 1 - 20 ma i o dc output sink current - 0.5 < v o 2000 mar 15 9 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 74ahct family over recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions t amb ( c) unit other v cc (v) 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih high-level input voltage 4.5 to 5.5 2.0 -- 2.0 - 2.0 - v v il low-level input voltage 4.5 to 5.5 -- 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il ; i o = - 50 m a 4.5 4.4 4.5 - 4.4 - 4.4 - v v i =v ih or v il ; i o = - 8.0 ma 4.5 3.94 -- 3.8 - 3.70 - v v ol low-level output voltage v i =v ih or v il ; i o =50 m a 4.5 - 0 0.1 - 0.1 - 0.1 v v i =v ih or v il ; i o = 8.0 ma 4.5 -- 0.36 - 0.44 - 0.55 v i i input leakage current v i =v ih or v il 5.5 -- 0.1 - 1.0 - 2.0 m a i oz 3-state output off-state current v i =v ih or v il ; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0 5.5 -- 0.25 - 2.5 - 10.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 4.0 - 40 - 80 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 1.35 - 1.5 - 1.5 ma c i input capacitance -- 310 - 10 - 10 pf 2000 mar 15 10 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 ac characteristics type 74ahc595 gnd = 0 v; t r =t f 3.0 ns. symbol parameter test conditions t amb ( c) unit waveforms c l 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v cc = 3.0 to 3.6 v; note 1 t phl /t plh propagation delay sh cp to q 7 see figs 7 and 12 15 pf - 5.7 13.0 1.0 15.0 1.0 16.5 ns propagation delay st cp to q n see figs 8 and 12 - 5.9 11.9 1.0 13.5 1.0 15.0 ns t phl propagation delay mr to q 7 see figs 10 and 12 - 5.9 12.8 1.0 13.7 1.0 15.0 ns t pzh /t pzl 3-state output enable time oe to q n see figs 11 and 12 - 5.6 11.5 1.0 13.5 1.0 15.0 ns t phz /t plz 3-state output disable time oe to q n - 5.4 11.0 1.0 13.0 1.0 14.5 ns t phl /t plh propagation delay sh cp to q 7 see figs 7 and 12 50 pf - 7.7 16.5 1.0 18.5 1.0 20.1 ns propagation delay st cp to q n see figs 8 and 12 - 7.7 15.4 1.0 17.0 1.0 18.5 ns t phl propagation delay mr to q 7 see figs 10 and 12 - 7.4 16.3 1.0 17.2 1.0 18.7 ns t pzh /t pzl 3-state output enable time oe to q n see figs 11 and 12 - 7.4 15.0 1.0 17.0 1.0 18.5 ns t phz /t plz 3-state output disable time oe to q n - 8.7 15.7 1.0 16.2 1.0 17.5 ns t w shift clock pulse width high or low see figs 7 and 12 5.0 -- 5.0 - 5.0 - ns storage clock pulse width high or low see figs 8 and 12 5.0 -- 5.0 - 5.0 - ns master reset pulse width low see figs 10 and 12 5.0 -- 5.0 - 5.0 - ns t su set-up time d s to sh cp see figs 8 and 12 3.5 -- 3.5 - 3.5 - ns set-up time sh cp to st cp see figs 9 and 12 8.5 -- 8.5 - 8.5 - ns t h hold time d s to sh cp 1.5 -- 1.5 - 1.5 - ns t rem removal time mr to sh cp see figs 10 and 12 3.0 -- 3.0 - 3.0 - ns f max maximum clock pulse frequency sh cp or st cp see figs 7, 8 and 12 80 125 - 60 - 40 - mhz 2000 mar 15 11 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 notes 1. typical values at v cc = 3.3 v. 2. typical values at v cc = 5.0 v. v cc = 4.5 to 5.5 v; note 2 t phl /t plh propagation delay sh cp to q 7 see figs 7 and 12 15 pf - 4.0 8.2 1.0 9.4 1.0 10.5 ns propagation delay st cp to q n see figs 8 and 12 - 4.2 7.4 1.0 8.5 1.0 9.5 ns t phl propagation delay mr to q 7 see figs 10 and 12 - 4.4 8.0 1.0 9.1 1.0 10.0 ns t pzh /t pzl 3-state output enable time oe to q n see figs 11 and 12 - 4.0 8.6 1.0 10.0 1.0 11.0 ns t phz /t plz 3-state output disable time oe to q n - 3.8 8.0 1.0 9.5 1.0 10.5 ns t phl /t plh propagation delay sh cp to q 7 see figs 7 and 12 50 pf - 5.4 10.0 1.0 11.4 1.0 12.5 ns propagation delay st cp to q n see figs 8 and 12 - 5.5 9.0 1.0 10.5 1.0 11.5 ns t phl propagation delay mr to q 7 see figs 10 and 12 - 5.6 10.0 1.0 11.1 1.0 12.0 ns t pzh /t pzl 3-state output enable time oe to q n see figs 11 and 12 - 5.3 10.6 1.0 12.0 1.0 13.0 ns t phz /t plz 3-state output disable time oe to q n - 5.8 10.3 1.0 11.0 1.0 12.0 ns t w shift clock pulse width high or low see figs 7 and 12 5.0 -- 5.0 - 5.0 - ns storage clock pulse width high or low see figs 8 and 12 5.0 -- 5.0 - 5.0 - ns master reset pulse width low see figs 10 and 12 5.0 -- 5.0 - 5.0 - ns t su set-up time d s to sh cp see figs 8 and 12 3.0 -- 3.0 - 3.0 - ns set-up time sh cp to st cp see figs 9 and 12 5.0 -- 5.0 - 5.0 - ns t h hold time d s to sh cp 2.0 -- 2.0 - 2.0 - ns t rem removal time mr to sh cp see figs 10 and 12 2.5 -- 2.5 - 2.5 - ns f max maximum clock pulse frequency sh cp or st cp see figs 7, 8 and 12 130 170 - 110 - 90 - mhz symbol parameter test conditions t amb ( c) unit waveforms c l 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. 2000 mar 15 12 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 type 74ahct595 gnd = 0 v; t r =t f 3.0 ns. note 1. typical values at v cc = 5.0 v. symbol parameter test conditions t amb ( c) unit waveforms c l 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v cc = 4.5 to 5.5 v; note 1 t phl /t plh propagation delay sh cp to q 7 see figs 7 and 12 15 pf - 3.8 8.2 1.0 9.0 1.0 10.0 ns propagation delay st cp to q n see figs 8 and 12 - 4.0 7.4 1.0 8.5 1.0 9.5 ns t phl propagation delay mr to q 7 see figs 10 and 12 - 4.6 8.2 1.0 9.5 1.0 10.5 ns t pzh /t pzl 3-state output enable time oe to q n see figs 11 and 12 - 4.8 9.0 1.0 11.0 1.0 12.0 ns t phz /t plz 3-state output disable time oe to q n - 3.6 6.9 1.0 8.0 1.0 9.0 ns t phl /t plh propagation delay sh cp to q 7 see figs 7 and 12 50 pf - 5.2 10.0 1.0 11.0 1.0 12.0 ns propagation delay st cp to q n see figs 8 and 12 - 5.3 9.0 1.0 10.5 1.0 11.5 ns t phl propagation delay mr to q 7 see figs 10 and 12 - 5.8 10.5 1.0 11.5 1.0 12.5 ns t pzh /t pzl 3-state output enable time oe to q n see figs 11 and 12 - 6.2 11.6 1.0 13.0 1.0 14.5 ns t phz /t plz 3-state output disable time oe to q n - 5.8 10.3 1.0 11.0 1.0 12.0 ns t w shift clock pulse width high or low see figs 7 and 12 5.0 -- 5.0 - 5.0 - ns storage clock pulse width high or low see figs 8 and 12 5.0 -- 5.0 - 5.0 - ns master reset pulse width low see figs 10 and 12 5.0 -- 5.0 - 5.0 - ns t su set-up time sh cp to st cp see figs 8 and 12 5.0 -- 5.0 - 5.0 - ns set-up time d s to sh cp see figs 9 and 12 3.0 -- 3.0 - 3.0 - ns t h hold time d s to sh cp 2.0 -- 2.0 - 2.0 - ns t rem removal time mr to sh cp see figs 10 and 12 3.0 -- 3.0 - 3.0 - ns f max maximum clock pulse frequency sh cp or st cp see figs 7, 8 and 12 130 170 - 110 - 90 - mhz 2000 mar 15 13 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 ac waveforms handbook, full pagewidth mna557 sh cp input q 7 ' output t plh t phl t w 1/f max v m (2) v oh v i gnd v ol v m (1) family v i input requirements v m (1) input v m (2) output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc fig.7 the clock (sh cp ) to output (q 7 ) propagation delays, the shift clock pulse width (t w ) and maximum shift clock frequency (f max ). handbook, full pagewidth mna558 st cp input q n output t plh t phl t w t su 1/f max v m (2) v oh v i gnd v ol v m (1) sh cp input v i gnd v m (1) fig.8 the storage clock (st cp ) to output (q n ) propagation delays, the storage clock pulse width (t w ) and the shift clock to storage clock set-up time (t su ). family v i input requirements v m (1) input v m (2) output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc 2000 mar 15 14 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 handbook, full pagewidth mna560 gnd gnd t h t su t h t su v m (1) v m (1) v m (2) v i v oh v ol v i q 7 ' output sh cp input d s input fig.9 the data set-up (t su ) and hold (t h ) times for the d s input. family v i input requirements v m (1) input v m (2) output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc the shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth mna561 mr input sh cp input q 7 ' output t phl t w t rem v m (2) v oh v ol v i gnd v i gnd v m (1) v m (1) family v i input requirements v m (1) input v m (2) output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc fig.10 the master reset ( mr) pulse width, the master reset to output (q 7 ) propagation delays and the master reset to shift clock (sh cp ) removal time (t rem ). 2000 mar 15 15 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 fig.11 3-state enable and disable times. family v i input requirements v m (1) input v m (2) output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc handbook, full pagewidth mna450 t plz t phz outputs disabled outputs enabled v oh - 0.3 v v ol + 0.3 v outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v i v cc v m (1) v ol v oh gnd gnd t pzl t pzh v m (2) v m (2) handbook, full pagewidth open gnd v cc v cc v i v o mna219 d.u.t. c l r t 1000 w pulse generator s1 fig.12 load circuitry for switching times. test s1 t plh /t phl open t plz /t pzl v cc t phz /t pzh gnd definitions for test circuit. c l = load capacitance including jig and probe capacitance (see chapter ac characteristics). r t = termination resistance should be equal to the output impedance z o of the pulse generator. 2000 mar 15 16 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 package outlines x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 97-05-22 99-12-27 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1 2000 mar 15 17 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1.0 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 95-04-04 99-12-27 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.10 pin 1 index 2000 mar 15 18 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2000 mar 15 19 philips semiconductors product speci?cation 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74ahc595; 74ahct595 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 613507/01/pp 20 date of release: 2000 mar 15 document order number: 9397 750 06822 |
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